1. Field of the Invention
The invention relates to a semiconductor memory device with a SRAM (Static Random Access Memory) configuration. Specifically, this invention relates to a semiconductor memory device in which in each memory cell, two transistor formation regions are disposed so as to extend in the same direction along which a bit line extends, respectively and a voltage potential supply line and a standard potential supply line are disposed parallel to the direction along which the bit line extends.
2. Description of the Related Art
A SRAM cell generally has a latch and two transistors (word transistors). On-off operations of the transistors are controlled based on the voltage applied to a word line and thereby connection between each of two memory nodes of the latch and a bit line is made or broken. The SRAM cells can be broadly divided into two types, namely a MOS transistor load type and a high resistance load type, based on a difference in the load element of the latch. The SRAM cell of the MOS transistor load type comprises two n-channel type MOS transistors in which the latch functions as a drive transistor (hereinafter referred to as nMOS transistor) and two p-channel type MOS transistors in which the latch functions as a load transistor (hereinafter referred to as pMOS transistor). In this SRAM, one CMOS inverter is composed of one n-MOS transistor and one pMOS transistor and the other CMOS inverter is composed of the other nMOS transistor and the other pMOS transistor. These two CMOS invertors are connected crossing each other and thereby a latch is formed.
This SRAM is not a charge holding type such as a random access memory (DRAM) but a current driving type by a latch so that high-speed access is possible. However, as high-speed operation in a microprocessor is realized, further high-speed operation in the SRAM is required.
In general, conventionally, the wiring structure of this type of SRAM cell is as follows. A polycrystalline silicon layer which will comprise a gate electrode is formed on a semiconductor substrate such as silicon. Node wiring as a first metal wiring layer, word wiring as a second metal wiring layer, voltage potential supply lines (power supply voltage line) and reference potential supply lines (grounded line) as a third metal wiring layer, bit lines as a fourth metal wiring layer and main word lines as a fifth metal wiring layer are stacked in sequence. The main word line is for inputting a common drive signal to a predetermined word line driver. When seen from above, the main word lines are formed in the most upper layer and the bit lines are formed between the main word line, and the power supply voltage line and the grounded line.
By the way, in this type of SRAM cell, generally signal delay in a bit line and a main word line occurs. One of the main reasons why delay in a bit line (referred to as bit line delay hereinafter) and delay in a main word line (referred to as main word line delay) occurs is because when pulling up or down the bit line and main word line, charge is also needed for parasitic capacity of the bit line and main word line. Duration of the wiring delay is almost equal to the amount of its wiring capacitance. Here, in the cell having the above-described configuration, in the bit line, parasitic capacity occurs both between the main word line in the upper layer and the bit line, and between the power supply voltage line and the grounded line in the lower layer and the bit line. On the other hand, in the main word line, parasitic capacity occurs between the bit line in the lower layer and the main word line. However, since there is no upper layer, parasitic capacity is smaller than that of the bit line. Consequently, when the bit line delay and main word line delay are compared, the bit line delay is larger than the main word delay by a difference of approximately 4:1 to 10:1.
In order to reduce the above-described bit line delay, preferably, the main word line is formed in the layer below the bit line. However, when the main word line is formed in the layer below the bit line, the main word line needs to be disposed avoiding a contact (bit line contact) corresponding to the bit line.
FIGS. 18A to 18C show the layout of a conventional SRAM in each step. In this SRAM, two bit line contacts 201a and 201b are formed on one side of a memory cell 200 in a rectangular shape as illustrate in FIG. 18A. On another side of the memory cell 200, a power supply voltage line contact 202a and a grounded line contact 202b are formed. Adjacent two memory cells 200 are disposed in mirror symmetry with one side as a boundary facing the side in which the bit line contacts 201a and 201b are formed. Each one of the bit line contacts 201a and 201b is arranged every two rows in a direction along which the bit line extends. Thus, in this SRAM there is enough space for a main word line to be disposed so as to avoid the bit line contacts 201a and 201b. FIG. 18B shows a state such that a main word line 204 in a rectangular shape is formed with bit line connection wires 203a and 203b. FIG. 18C shows a state such that bit lines 205a and 205b are formed so as to be connected to bit line connection wires 203a and 203b in the layer above the main word line 204. That is, in the memory cell 200, by forming the main word line 204 in a rectangular shape, sufficient width is secured and thereby sufficiently low resistance can be obtained.
Incidentally, another type of SRAM exists such that by shortening a bit line, its capacity and resistance is reduced, thereby improving access speed. This type of SRAM has a layout illustrated in FIG. 19, for example.
This SRAM cell is a split word line type. In the SRAM, each memory cell 300 includes two p-type active regions 301a and 301b in which an n-channel MOS transistor as a drive transistor will be formed, and two n-type active regions 302a and 302b in which a p-channel MOS transistor as a load transistor will be formed. The two p-type active regions 301a and 301b have a step 306, respectively and are disposed parallel to each other in a vertical direction in the figure. In the p-type active region 301a, a drive transistor Qn1 and a word transistor Qn3 are formed sandwiching the step 306 in between. In the p-type active region 301b, a word transistor Qn4 and a word transistor Qn2 are formed sandwiching the step 306 in between. A word line 304a (WL1) serving also as a gate electrode for the word transistor Qn3 is disposed orthogonal to the p-type active region 301a. A word line 304b (WL2) serving also as a gate electrode for the word transistor Qn4 is disposed orthogonal to the p-type active region 301b. A common gate line 305a (GL1) serving also as a gate electrode for the drive transistor Qn1 is placed orthogonal to the p-type active region 301a in a vertical direction in the figure. A common gate line 305b (GL2) serving also as a gate electrode for the drive transistor Qn2 is placed orthogonal to the p-type active region 301b in a vertical direction in the figure. The common gate lines 305a and 305b and word lines 305a and 305b are formed of a polycrystalline silicon layer as a first layer including impurities.
The common gate line 305a is also orthogonal to the n-type active region 302a. The common gate line 305b is also orthogonal to the n-type active region 302b. As s result, pMOS (load transistor Qp1 or Qp2) is formed in the n-type active regions 302a and 302b, respectively. A first inverter is composed of the load transistor Qp1 and the drive transistor Qn1. A second inverter is composed of the load transistor Qp2 and the drive transistor Qn2. The first inverter and the second inverter comprise a latch.
The p-type active regions 301a and 301b are electrically coupled to the bit line through bit line contacts 307a and 307b and to a grounded line (common potential supply line) Vss through grounded line contacts 308a and 308b, respectively. The p-type active region 301a and n-type active region 302a, and the p-type active region 301b and n-type active region 302b are electrically coupled to each other through contacts (not shown). The n-type active regions 302a and 302b are electrically coupled to a voltage potential supply line Vcc through power supply voltage line contacts 309a and 309b, respectively.
In this SRAM cell, the nMOS transistor formation region (p-type active regions 301a and 301b) in which an n-MOS transistor will be formed, and the pMOS transistor formation region (n-type active regions 302a and 302b) in which a pMOS transistor will be formed are disposed in the same direction (in the horizontal direction in FIG. 19) as the direction along which the bit line (not shown) extends. Therefore, the bit line is shortened and its capacity and resistance is reduced, thereby improving access speed.
However, in this conventional SRAM cell shown in FIG. 19 each one of the bit line contacts 307a and 307b are placed in one row and bit line contacts 307a and 307b are disposed in a different position in the cell in a direction along which the bit line extends. Moreover, the width H of one row is narrow, about half of the layout of the conventional SRAM cell. Therefore, in a case where the main word line is formed in the layer below the bit line as described above, if the main word line has a rectangular shape as the conventional memory cell, sufficient width with sufficiently low resistance cannot be obtained. More specifically, in the SRAM cell with the layout shown in FIG. 19, although the bit line can be shortened in each cell, it is difficult to reduce bit line delay caused by wiring parasitic capacity between the bit line and the main word line, thus high-speed operation is not possible.
This invention is designed to overcome the foregoing problems. It is an object of the invention to provide a semiconductor memory device having a configuration such that an n-MOS transistor formation region and a PMOS transistor formation region are formed so as to extend in the same direction along which a bit line extends, so that bit line delay caused by wiring parasitic capacity can be reduced and high-speed operation is realized.
According to the present invention, in a semiconductor memory device including in each memory cell a first and second nMOS transistor connected crossing over each other and a first and second pMOS transistor which are respectively connected between a drain of the NMOS transistor and a power supply voltage line. An nMOS transistor formation region in which the first and the second nMOS transistor will be formed, and a pMOS transistor formation region in which the first and the second pMOS transistor will be formed are disposed in the same direction along which the bit line extends, respectively. Formed in the layer below the bit line is a main word line which inputs a common drive signal to a predetermined word line driver. Moreover, the main word line is arranged so as to avoid a bit line contact which electrically connects the bit line and a transistor region disposed in the layer below the main word line.
In the semiconductor memory device according to the present invention, since the main word line is formed so as to avoid the region where the bit line contact is formed, the main word line can be formed in the layer below the bit line, and delay (bit line delay) caused by wiring parasitic capacity between the bit line and the main word line is eliminated. As a result, high-speed operation in the memory cell is made feasible in the bit line.
Other and further objects, features and advantages of the invention will appear more fully from the following description.